Coding Tree Structure
The below images indicate how the large homogenous or less detailed areas are covered by large block sizes ranging from 64x64 to 8x8 and the detailed regions are hierarchically broken down to ensure the variations are divided into smaller areas to enable better prediction as well as residual coding.
Figure 1 a: Part of a sample frame from a sequence of video frames
Figure 1 b: Frame from figure 1 a with Coding Units (CU) overlaid to indicate HEVC coding structure
Enhanced Prediction Modes
Figure 2: Types of Inter prediction units in HEVC
Additional in-loop filtering options
Improved Parallel Processing
Advent of higher SIMD (Single Instruction and Multiple Data) architectures like AVX/AVX2.0 from Intel and NEON from ARM along with 64 bit processing has enabled better throughputs for complex pixel processing operations. Larger transform and prediction sizes can be programmed to have higher throughput on both load/stores as well as for arithmetic operations, enabling better processing on these architectures.
Figure 3: Indicates staggering in time of CTB processing across rows to handle prediction dependencies
HDR, Range Extensions and Color Primaries