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802.11b PHY IP Core 802.11b PHY IP Core is a licensable and synthesizable HDL implementation of IEEE Standard 802.11b 1999 Edition in VHDL/Verilog. The IEEE 802.11b specification is the high rate extension of the Physical Layer for the Direct Sequence Spread Spectrum (DSSS) system (as per IEEE Standard 802.11 - 1999) for the 2.4 GHz band designated for ISM applications. This extension of the DSSS system builds on the data rate capabilities of 802.11 to provide 5.5 and 11 Mbps payload data rates in addition to the 1 and 2 Mbps rates. To provide the higher rates, 8 chip Complementary Code Keying (CCK) is employed as the modulation scheme with the chipping rate of 11 MHz thus providing the same occupied channel bandwidth. In addition to providing higher speed extensions to the DSSS system, a number of optional features are described that will allow the performance of the Wireless LAN system to be improved. An optional mode replacing the CCK modulation with Packet Binary Convolutional Coding (PBCC) is provided. Another optional mode, which allows data throughput at the higher rates (2, 5.5 and 11 Mbps) to be significantly increased by using a shorter PLCP preamble is also provided. Technical Specification
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